Instruction Cycle in Computer Architecture

The Instruction Cycle is the complete process in which a computer fetches, decodes, executes, and sometimes stores the result of an instruction. This cycle is repeated for each instruction in a program.

---

Phases of the Instruction Cycle:

1. Fetch Cycle:

• The Program Counter (PC) contains the address of the next instruction.
• The address is sent to Memory to fetch the instruction.
• The fetched instruction is stored in the Instruction Register (IR).
• The PC is incremented to point to the next instruction.

Example:

PC → MAR       ; Program Counter address moved to Memory Address Register
MEM[MAR] → MDR ; Data fetched from memory into Memory Data Register
MDR → IR       ; Data moved to Instruction Register
PC = PC + 1    ; Increment Program Counte

---

2. Decode Cycle:

• The Control Unit (CU) reads the instruction from the IR.
• It interprets the opcode (operation code) to understand the action required.
• The operands and addressing modes are identified.

Example:

IR → CU             ; Instruction decoded by Control Unit
Opcode → Operation  ; Identify the operation (e.g., ADD, MOV)
Operands → Addressing Mode Interpretation 3.

---

3. Execute Cycle:

• The ALU (Arithmetic Logic Unit) or relevant hardware executes the operation.
• Operations can be arithmetic (ADD, SUB), logical (AND, OR), or data transfer.
• If required, memory or register content is read or modified.

Example:

ADD AX, BX         ; AX = AX + BX
MOV CX, 1000       ; Move value 1000 to CX4. 

---

4. Memory Access (Optional):

• If the instruction involves memory read/write, this phase is triggered.
• Data is either fetched from or stored into the specified memory location.

Example:

LOAD AX, [1000]    ; Load the value at address 1000 into AX
STORE AX, [2000]   ; Store the value of AX into address 2000

---

5. Write Back (Optional):

• If the operation produces a result, it may need to be stored back to memory or a register.
• This step is skipped for instructions like JMP or NOP.

Example:

MDR → [Address]    ; Move data from Memory Data Register to memory
AX → [2000]        ; Store the result in memory location 2000

---

6. Interrupt Check (Optional):

• At the end of each cycle, the CPU checks if there are pending interrupts.
• If an interrupt exists, the CPU executes the Interrupt Service Routine (ISR) before the next instruction cycle.

---

Graphical Representation of the Instruction Cycle:

+------------------+      +------------------+      +------------------+
|   Fetch Cycle   | ---> |   Decode Cycle   | ---> |   Execute Cycle  |
+------------------+      +------------------+      +------------------+
        |                       |                       |
        V                       V                       V
+------------------+      +------------------+      +------------------+
|   Memory Access | ---> |   Write Back    | ---> | Interrupt Check  |
+------------------+      +------------------+      +------------------+

---

Summary Table:

Phase	Purpose	Registers Used
Fetch	Get the instruction from memory	PC, MAR, MDR, IR
Decode	Interpret the instruction	IR, CU
Execute	Perform the operation	ALU, Registers
Memory Access	Read/write data if needed	MAR, MDR
Write Back	Store the result back	Registers, Memory
Interrupt Check	Check for and handle interrupts	Interrupt Register (if any)